1. Field of the Invention
The present invention relates to dynamic random-access memories (RAMs), and more particularly to a method of producing one-transistor cells for dynamic RAMs.
2. Description of the Prior Art
There are various well-known structures of one-transistor cells for dynamic random-access memory (RAM) integrated circuits (cf. V. Leo Rideout, "One-Device Cells for Dynamic Random-Access Memories," IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, PP. 839-852, June 1979). A memory cell consists of a transistor (a MOSFET switch) and a charge storage capacitor having an area S. The charge capacitance C of the capacitor consists of an MOS capacitance Co and a junction capacitance Cs and is expressed by means of the following formula. EQU C=CO+Cs
It is possible to increase the charge capacitance C by increasing the area S of the charge storage capacitor. However, an increase of the area S involves an increase of the area of the memory cell, so that the cell density is lowered. It is also possible to increase the charge capacitance C by increasing the junction capacitance Cs without increasing the cell area. The junction capacitance Cs is expressed by means of the following formula: EQU Cs=(.epsilon.s.S)/(W)
wherein .epsilon.s is the dielectric constant of silicon, assuming a silicon device, and W is the thickness of the depletion layer. Accordingly, an increase of the junction capacitance Cs can be attained by decreasing the thickness W. As illustrated in FIG. 1 the decrease in the depletion layer thickness W is carried out by forming a shallow n.sup.+ -type region 2 and a deeper p.sup.+ -type region 3 which lie under a capacitor electrode plate 4 in a p-type silicon substrate 1. The structure of a one-transistor memory cell illustrated in FIG. 1 is almost the same as that of the one-transistor memory cell illustrated in FIG. 15 on page 848 of the above-mentioned reference.
In the one-transistor memory cell of FIG. 1, an MOS capacitance Co is formed by the capacitor electrode plate 4, a thin oxide (SiO.sub.2) layer 5 and the n.sup.+ -type region 2, and a junction capacitance Cs is formed by the n.sup.+ -type region 2 and the p.sup.+ -type region 3. The reference numerals 6, 7 and 8 represent a field oxide (SiO.sub.2) layer, a first insulating layer (e.g. an SiO.sub.2 layer) and a second insulating layer (e.g. a PSG layer), respectively. An n.sup.+ -type region 9 of a bit line is formed in the silicon substrate 1 and a transfer gate 10 connected to a conductor layer 11 of a word line is formed on the first insulating layer 7. With regard to the structure of the one-transistor memory cell of FIG. 1, it is important that the n.sup.+ -type region 2 overlaps the p.sup.+ -type region 3, namely, that an end portion 2a of the n.sup.+ -type region 2 extend further than an end portion 3a of the p.sup.+ -type region 3, as illustrated in FIG. 1. The n.sup.+ -type and p.sup.+ -type regions 2 and 3 are respectively formed by doping n-type impurities and p-type impurities by ion implantation or thermal diffusion. If the doping steps for the regions 2 and 3 are carried out by using a masking step, as illustrated in FIG. 2, the end portion 3a of the p.sup.+ -type region 3 covers the end portion 2a of the n.sup.+ -type region 2, since the diffusion length of p-type impurities is deeper than that of n-type impurities in the silicon substrate 1. Therefore, an inversion layer does not occur easily at a surface portion 3b of the end portion 3a of the p.sup.+ -type region 3. Namely, a potential barrier occurs at the end portion 3a to prevent a charge from leaving the capacitor C.
The occurring of the potential barrier can be prevented by performing two masking steps for doping of n-type impurities and p-type impurities. Since two masks are used in the two masking steps, it is necessary to provide a margin for aligning one of the masks to a pattern formed by the other mask. Such a margin prevents the cell area from being decreased and the cell density from being increased.